D A T A O D Y S S E Y
FOR S O L U T I O N S I N H A R D A N D S O F T W A R E
Autobias and Error Feedback for MOSFET and BJT Audio Output Stages
Fig.1 Basic Auto Bias circuit with Error Feedback
(click to enlarge)
As was the previous auto-bias arrangements just a replacement for a thermally coupled Vbe multiplier, this new circuit does a few more things: It not only provides a well defined bias, including temperature compensation of the output devices, but also a sliding (also called adaptive) bias, which prevents the output stage from entering into class-B operation. As a result, the output devices are never completely turned off. In case of BJT output stage the typical nasties of the 'hole-storage' effect are thus avoided.
The idea of a sliding bias is certainly not new, see the references. However, opposed to many other proposed circuits, this circuit is quite simple (in its simplest form a dual complementary VAS and two chips with a few matched transistors). Furthermore, it's bloody fast and the relationship between the currents of top and bottom output transistor is fully symmetrical. As for the latter, It should be noticed that this is not always the case with similar designs that were proposed up to now.
Since the sensing transistors Q3...Q6 operate at a very low voltage (0.7V), the circuit lends itself well to applications with BJTs or low threshold MOSFETs as output devices.
Last but not least, the circuit provides effective means for error feedback at no additional cost: Instead of feeding the input signal via the current sources (in other words, use them as VAS as well), simply feed the input signal at the emitter junction of Q1 and Q2. This way the distortion is reduced by an order of magnitude.
A little bit of math
First, these calculations are an approximation, as the effects of the finite beta, Early voltage, bulk resistance etc. are neglected.
At full (positive) excursion of the amp, it is assumed that M1 carries such a large current that Q5 is turned off and M2 carries a minuscule current (for the moment), so that Q6 is maximally turned on. Under these conditions the following holds:
I3 + I5 = I4 + I6 = IB = 4mA (1)
I3 = 4mA and I5 = 0 (2)
I4 = I6 = 2mA (3)
From (2) and (3) it follows that:
I1 = I2 = IA = sqrt(2*4) ~= 2.83mA (4)
However, choosing IA = 2.83mA is not a good idea, as due to component tolerances, much chance that the bias voltage collapses (during large excursions) and one the output devices gets completely turned off.
Therefore we set IA a little higher, say 3mA, to be on the safe side.
Now that IA is also defined, we can calculated the appropriate values of R1 and R2 for a given quiescent current (IQ), as well as the minimum drain current of M1 and M2.
At quiescent condition:
I5 = I6 = IB - IA = 4-3 = 1mA (5)
From (1) and (5) it follows that:
Vs1 = Vs2 = Vbe(Q4) - Vbe(Q6) = VT ln( I4 / I6 ) = VT ln 3 = 28.5mV (6)
For IQ = 150mA R1 = R2 = 28.5 / 150 = 0.19 Ohm
Calculation of the minimum drain current
Going back to a full positive excursion, than:
I1 = I2 = 3mA, I3 = 4mA, I5 = 0 & I4 + I6 = 4mA
I1 = sqrt( I3 * I4 ), see also (4)
I3 * I4 = 3mA ^ 2 ----> I4 = 9/4 mA = 2.25mA
I6 = 4 - 2.25 = 1.75mA
Vs2 = VT ln (2.25/1.75) = 6.5mV
So the minimum Id = 6.5 / 0.19 = 34.4mA
Notice that the bias current depends on VT (i.e. ~0.3% / K), that is, it depends on the temperature of the matched transistor Q1...Q6 (same as the LT1166, by the way).
Disclaimer: Above circuit does NOT include all necessary protection measures, neither frequency compensation to ensure stable operation under all possible conditions. The information as provided here is preliminary and subject to changes. So be warned, especially 'the inexperienced hobbyist'.
1. Kazuaki Nakayama, "Emitter-Follower Type Single-Ended Push-Pull Circuit", US patent 4595883, 06-17-1986.
2. M.O.J. Hawksford, "Error Correction and Non-Switching Power Amplifier Output Stages", 102nd AES Convention, Munich, March 1997, preprint 4492
3. D. Danyuk & M.J. Renardson "Error Correction in Class AB Power Amplifiers', paper presented at the 114th AES Convention, March 22–25 2003
Amsterdam, The Netherlands. See also: http://www.angelfire.com/ab3/mjramp/pagefour.html
4. Dipl.-Ing. Walter Meusberger, dissertation, "A Novel Power Amplifier Topology without Crossover distotion", Graz, October 1999.
5. Datasheet LT1166, "Automatic bias system", Linear Technology
Fig.2 Source current as function of Vout (RL=16 Ohms)
Fig.3 Harmonic distortion products at 20kHz (full scale = 10ppm)
Fif. 4. Frequency and phase response of the ouput stage
Fig. 5. Step response. Slew rate is pretty high and apparently not impaired by the bias circuit.
Above the relationship of source currents vs output voltage and the harmonic distortion of the output stage of fig.1. THD-20k is about 0.01%.
Below the frequency, phase and step response of a more realistic output stage, including frequency compensation and several catch diodes to project the bias transistors against overload conditions and reverse voltages.
Comparison with a few other techniques
First, let's start with a (hypothetical) technique that keeps the product of drain currents at a fixed level. So Idp * Idn = c. The relationship between these currents versus the output current is depicted by the blue curve in the next graph.
The auto bias chip from Linear Technology, the LT1166, is advertised to do exactly that. However, a simulation, based on a model at the device level, reveals a different picture, see the red curves. Clearly, the minimum Id is kept well above a certain level. So Idp * Idn is not held constant (not that it really matters).
Now, let's look at the properties of the newly proposed circuit. This one also doesn't comply with the 'constant product objective', though it comes a bit closer. See the green curves.
For a number of different bias schemes the harmonic distortion has been investigated. This time the bias generator has been embedded in a complete though simple amplifier. In order to not blur the THD figures, the input stage, complementary VAS and drivers consist of ideal (read: distortionless) components, like a CCS, VCCS, CCCS and VCVS. The bias generator consist of 'real virtual' components (of course) as well as the OPS, in this case of only one pair of vertical MOSFETs. The following variants were simulated:
1. Constant bias voltage (CBV)
2. Constant Drain current product (CDCP)
3. Dito, based on the LT1166 (LT1166)
4. New bias circuit without error feedback (AB2)
5. Dito, however with error feedback (AB2EC)
6. Improved version of #5 (AB2ECV4)
Frequency: 20Hz 1kHz 20kHz
CBV: 0.08 4.2 94
CDCP: 0.12 5.9 120
LT1166: 5.8 8.1 117
AB2: 0.15 7.4 150
AB2EC: 0.016 0.43 10.2
AB2ECV4: 0.002 0.011 3.1 preferred
(THD figures are in ppm. Click on the hyper links to see the schematics.)
(to be continued when I'm in the mood)
Fig. 8. Drain currents vs output current.
blue: Idp * Idn = c, red: LT1166, green: new circuit.
Fig. 6. Frequency and phase response of the error feedback loop. Phase margin = 90 degrees; ULGF = 3MHz.
Fig. 7. Frequency and phase response of the bias feedback loop. Phase margin = 60 degrees; ULGF = 1MHz.
Fig. 9. Harmonic distortion products at 20kHz of amplifier AB2EC. THD = 11ppm (bandwidth = 500kHz, full scale = 10ppm)
Fig. 10. Harmonic distortion products at 20kHz of amplifier AB2ECV4. THD = 3.6ppm (bandwidth = 500kHz)